Design Verification

1.0 SOA Check

This utility allows the user to rapidly input the maximum voltages/currents that are permissible per device and centralize these checks in a scalable template file. These checks can be used at a later point of time by each designer to verify that the SOA (safe operating areas) of all the devices in his/her DUT (Design Under Test) are adhered to. This methodology is PDK (process design kit) agnostic, does not require any edits to the model file, and requires no language coding skills to adopt. This tool will ensure that the passive/active devices in the DUT do not exceed their thresholds…

Hot Carrier Injection
Forward Biased
1.8v pmos to 1.8v Rail
bjt active mode

1.1 Hierarchy Check (Run Prior to SOA)

Hierarchy in circuit design refers to the creation of higher level cells based on lower leaf cells. This utility will hierarchically verify that the pointers to each instance are correct, cells are checked in, reports cell count, displays tree view, checks for unused cells, flagged views, and reports cellnames that clash with standard cell libraries. By default, it will also report cells that have missing links and/or are magnified. The hierarchy explorer is compatible with both cadence CDBA/OA and can be executed hierarchically on Layout/Schematic df2 views.

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